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16bit_display8bitLED
- Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. In
XHDL3Version3·2·37
- vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages
Alarm
- 用verilog HDL 写的时钟程序，在DE2上实现了。-Alarm program based on Verilog HDL, run on DE2 Board
Verilog_led
- DE2实验开发板的将32位数据转换为八个七段译码并显示-Experimental DE2 development board will be 32-bit data is converted to the eight and seventh decoding and display
DE2_70_TV
- --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor shoul
DE2_LCM_TV_NTSC
- DE2上的基于FPGA视频开发资料第二部分-DE2 video
DE2_SD_Card_Audio(Modified)
- 在DE2开发板上实现的SD卡mp3音乐播放器。硬件部分用Verilog语言编写，在Quartus上编译；软件部分用C语言编写，在Nios2上编译运行。-DE2 development board in the realization of the SD card mp3 music player. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run
DE2_NET
- 用DE2开发板实现的网络控制器。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。程序已经过测试，功能完好。-DE2 development board with the realization of the network controller. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in
TrackingPresentation_jon
- presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board wi
DE2_TV_PAL
- video信号pal制转vga输出，fpga verilong语言编写-fpga pal to vga ，writed in verilog
ITU_656_Decoder
- Aletra DE2开发板 ITU_656_Decoder-ITU_656_Decoder
DE2_LED_ON
- 一个简单的led闪烁程序，检测DE2学习板的led灯，用verilog语言编写-A simple blinking led program to petect learning DE2 board led lights, with the verilog language
DE2_SD_Card_Audio
- 在DE2实现SD卡音乐播放器 编写语言verilog-In the DE2 SD Card music player to achieve the preparation of language verilog
Watch
- Design Watch with set time by Verilog for kit DE2
DigitalWatch
- Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
TRDB_LCM
- DE1/DE2的TRDB_LCM驱动Verilog源代码。-DE1/DE2 of TRDB_LCM drive Verilog source code.
DE2_lab_exercises
- Altera DE2 原装光盘附带 案例教程 手把手教 十个实验 verilog hdl/vhdl-DE2_labs_ exercise with verilog/vhdl
FPGA
- 本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP
cam
- It is a VERILOG program for interfacing the 5Megapixel camera module in ALTERA DE2 CYCLONEII board.
IIC1
- i2c verilog code for de2 board